1. Field of the Invention
The present invention relates to a technique of extracting a synchronous clock signal from input data in an LSI at the receiving end in the serial transmission of data between LSIs.
2. Description of Related Art
With the progress of semiconductor technology, data transmission between LSIs is serialized. In order to reduce electromagnetic interface (EMI) in the serial data transmission, there is known a technique of performing frequency modulation using a spread spectrum clock in an LSI at the transmitting end and then extracting a clock from frequency-modulated serial data by a clock and data recovery circuit in an LSI at the receiving end (cf. Japanese Unexamined Patent Application Publication Nos. 2005-5999 and 2006-80991)
FIG. 11 is the illustration shown in FIG. 1 of Japanese Unexamined Patent Application Publication No. 2005-5999, and it shows the clock and data recovery circuit which is disclosed therein. The clock and data recovery circuit includes a phase detector 101, an integrator 102, an integrator 103, a pattern generator 104, a mixer 105, and a phase interpolator 106. The phase detector 101 compares the phase of input serial data with the phase of a clock signal which is output from the phase interpolator 106 and outputs a comparison result. Based on the comparison result, a frequency tracking loop which is formed by the integrator 103 and the pattern generator 104 tracks the phase shift at low frequencies or the frequency shift, and a phase tracking loop which is formed by the integrator 102 tracks the phase shift at high frequencies which cannot be tracked by the frequency tracking loop. The mixer 105 mixes the results of the frequency tracking loop and the phase tracking loop. Based on the mixture result, the phase of the synchronous clock signal which is output from the phase interpolator 106 is controlled, thereby extracting the synchronous clock of the serial data.
The phase detector 101 detects a difference in phase between the serial data and the synchronous clock signal and outputs an up signal or a down signal which indicates the difference as a comparison result. The integrator 102 and the integrator 103 are up/down counters that smooth the comparison result and output them as control signals. The integrator 102 and the integrator 103 each have a predetermined count width. The pattern generator 104 generates a control signal UP4/DOWN4 for correcting the frequency of the clock signal based on the control signal UP3/DOWN3 which is output from the integrator 103.
FIG. 12 is the illustration shown in FIG. 10 of Japanese Unexamined Patent Application Publication No. 2005-5999, and it shows another clock and data recovery circuit which is disclosed therein. The clock and data recovery circuit is different from the clock and data recovery circuit shown in FIG. 11 in that the frequency tracking loop and the phase tracking loop share the integrator 102.
FIG. 13 is the illustration shown in FIG. 7 of Japanese Unexamined Patent Application Publication No. 2005-5999, and it shows the configuration of the pattern generator 104 which is used in the above-described two clock and data recovery circuits. The pattern generator 104 includes a counter 141 that receives a clock signal and repeatedly counts from 0 to a predetermined upper limit in synchronization with the clock, an up/down counter 142 that receives the control signal UP3/DOWN3 from the integrator 103 which is formed by an up/down counter and the clock signal and counts up or counts down, and a decoder 143 that receives and decodes the count values from the counter 141 and the up/down counter 142 and outputs it as a result of the frequency tracking loop.
The inventor of the present invention has studied the performance of the frequency tracking loop in the circuits shown in FIGS. 11 and 12 and found the followings.
FIG. 10 shows the jitter tolerance characteristics (which is referred to simply as jitter tolerance) of the circuit shown in FIG. 12 in the case where the count width m of the integrator 102 is 5. In the example shown in FIG. 10, the pattern length p of the pattern generator 104 is 32.
In this case, the jitter tolerance of the circuit shown in FIG. 12 drops abruptly to the jitter at a certain frequency in the intermediate frequency band as shown in FIG. 10.
Due to the existence of such an abrupt drop, the performance of the frequency tracking loop is unstable, which causes failure in extracting an appropriate synchronous clock signal from serial data.